The present invention relates to semiconductor devices in which a junction termination extension region is utilized to increase the breakdown voltage of the device, and more particularly to a process for fabricating a junction termination extension region.
The maximum reverse voltage that a semiconductor device can withstand is often limited by the breakdown voltage of a reverse-blocking junction included in the device. Such a blocking junction may comprise, for example, a P-N junction of a thyristor, a bipolar transistor, an insulated-gate transistor, or a corresponding junction in a metal-oxide-semiconductor field-effect transistor. Such a blocking junction may also comprise a Schottky barrier rectifying junction in a diode or other device utilizing such a Schottky junction.
To increase the actual breakdown voltage of the P-N variety of blocking junctions in semiconductor devices, so-called junction termination extension (JTE) regions have been incorporated into the devices near a terminated portion of the P-N junction. A JTE region may in general be considered as a more lightly doped extension of a heavity doped semiconductor region that adjoins a lightly doped semiconductor region to form the foregoing P-N junction. The principal function of a JTE region is to reduce the high concentration of electric fields that would otherwise exist in the vicinity of the terminated portion of the P-N junction.
A two-zone JTE region has been described with predicted beneficial results in a report by V. A. K. Temple, entitled "Advanced Light-Triggered Thyristor", EPRI EL-3643, Project 669-2, Final Report (August 1984), pages 8-1 through 8-14. The use of multiple zones in a JTE region achieves the beneficial result of reducing both bulk and surface electric fields in a device protected with a JTE region. This results in an increase in the permissible variance of an implant dose for forming a JTE region, while assuring a high manufacturing yield of devices attaining a high breakdown voltage. Accordingly, the use of multiple zones in a JTE region accommodates uncertainties resulting from further device processing that affect the electrical properties of a JTE region.
While the two-zone JTE region in a semiconductor device as described in the foregoing Temple report predicts beneficial results, it is described in the report as entailing the use of two separate masks to form the two-zone JTE region. The use of multiple masks in device fabrication increases device cost, while decreasing device manufacturing yield, due to mask misalignments that are difficult to avoid.
Accordingly, it would be desirable to provide a single mask capable of being used to form a JTE region with multiple zones.